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Chapter 6: Board Test System
Preparing the Board
6–3
1
The Board Test System and Power Monitor share the JTAG bus with other
applications like the Nios II debugger and the SignalTap ? II Embedded Logic
Analyzer. Because the Quartus II programmer uses most of the bandwidth of the
JTAG bus, other applications using the JTAG bus might time out. Be sure to close the
other applications before attempting to reconfigure the FPGA using the Quartus II
Programmer.
Preparing the Board
With the power to the board off, following these steps:
1. Connect the USB cable to the board.
2. Verify the settings for the board settings DIP switch banks (SW1, SW2, and SW4)
match Table 4–1 on page 4–3 , Table 4–2 on page 4–4 , and Table 4–3 on page 4–5 .
3. Set the PGM CONFIG SELECT rotary switch (SW5) to the 1 position.
4. Verify the settings for the jumpers match Table 4–4 on page 4–6 . These settings
determine the devices to include in the JTAG chain, among other important
default settings.
f For more information about the board’s DIP switch and jumper settings,
refer to the Stratix IV E FPGA Development Board Reference Manual .
5. Turn the power to the board on. The board loads the design stored in the user
hardware portion of flash memory into the FPGA. If your board is still in the
factory configuration or if you have downloaded a newer version of the Board Test
System to flash memory through the Board Update Portal, the design loads the
GPIO, SRAM, and flash memory tests.
c
To ensure operating stability, keep the USB cable connected and the board
powered on when running the demonstration application. The application
cannot run correctly unless the USB cable is attached and the board is on.
Running the Board Test System
To run the application, navigate to the <install
dir> \kits\stratixIVE_4se530_fpga\examples\board_test_system directory and run
the BoardTestSystem.exe application.
1
On Windows, click Start > All Programs > Altera > Stratix IV E FPGA Development
Kit < version > > Board Test System to run the application.
A GUI appears, displaying the application tab that corresponds to the design running
in the FPGA. The Stratix IV E FPGA development board’s flash memory ships
preconfigured with the design that corresponds to the Config , GPIO , and SSRAM
and Flash tabs.
June 2011
Altera Corporation
Stratix IV E FPGA Development Kit User Guide
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